(1) Field of the Invention
The present invention generally relates to a semiconductor storage device, and more particularly to a semiconductor storage device having a sense amplifier for amplifying data read out from a memory cell to a bit line (a data line), wherein the sense amplifier is made of a circuit, such as a CMOS inverter, through which a current does not steadily pass.
(2) Description of the Related Art
Conventionally, a semiconductor storage device, for example, of a static random access memory (SRAM) having a current detection type sense amplifier in which a differential amplifier is used has been known.
This current detection type sense amplifier has a superior driving function. Thus, even if bit lines are extended upon increasing of a chip area and capacity so that the wire load of the bit lines and gate load of transistors connected to the bit lines are increased, a reading operation can be carried out at a high speed.
However, a large amount of current steadily flows through a differential amplifier forming the current detection type sense amplifier. Thus, there is an disadvantage in that the dissipation power of the sense amplifier is increased.
On the other hand, a current does not steadily flow through a CMOS inverter formed of a P-MOS transistor and a n-MOS transistor in a case where an input thereof is either in a high level state (H) or in a low level state (L). Thus, if the sense amplifier is formed using the CMOS inverter, the dissipation power thereof can be reduced.
However, because the CMOS inverter has a poor driving function and the reading operation cannot be carried out at a high speed, the CMOS inverter is conventionally used as the sense amplifier of the SRAM having a small capacity but is not suitable for the SRAM having a large capacity.
In a case where the bit lines are extended upon increasing of the capacity of the SRAM, the memory matrix (the memory cell array) may be divided. That is, the bit lines may be divided. If each of the divided bit lines is provided with the CMOS inverter as the sense amplifier, the load for each sense amplifier can be decreased. Thus, in this case, even if the CMOS is used as the sense amplifier, the reading operation can be carried out at a high speed.
In recent years, SRAMs, in each of which the sense amplifier is formed of the CMOS inverter so that the dissipation power of the sense amplifier can be reduced, have been greatly developed.
Recently, the SRAM having the sense amplifier formed of the CMOS inverter has been proposed, as shown in FIG. 1.
Referring to FIG. 1, a chip body 1 (a SRAM body) has a memory matrix 2 in which memory cells are arranged, a address register 3 for receiving address signals supplied from an external unit, a row decoder 4, a word line buffer 5, a column decoder 6, a sense amplifier circuit 7, an output data buffer 8 for outputting data from the sense amplifier circuit 7 as output data Dout to an external unit, an input data register 9 for receiving input data Din supplied from an external unit, a write amplifier 10, a column selector 11, a clock buffer 12 for receiving a clock signal supplied from an external unit, a pulse generator 13 for generating a predetermined pulse signal based on the clock signal received by said clock buffer 12 and a WE register 14 for receiving a write enable signal WE used for the write control. A row address signal included in the address signal received by the address register 3 is decoded by the row decoder 4, and a word line selecting signal is output from the row decoder 4. The word line buffer 5 drives word lines arranged in the memory matrix 2 based on the word line selecting signal output from the row decoder 5. A column address signal included in the address signal received by the address register 3 is decoded by the column decoder 6, a column selecting signal being output from the column decoder 6. The sense amplifier 7 amplifies and outputs data in memory cells coupled to a column (a bit line) identified by the column selecting signal output from the column decoder 6, among memory cells identified by the same row address in the memory matrix 2. The input data Din received by the input data resister 9 is written in the memory matrix 2 by the write amplifier 10. In the writing operation, the column selector 11 selects a column (a bit line) based on the column selecting signal output from the column decoder 6.
Each of the memory cells in the SRAM shown in FIG. 1 is formed as shown in FIG. 2. Referring to FIG. 2, a memory cell is coupled to writing word lines WWL and /WWL, reading word lines RWL and /RWL, a writing bit line WBL, and a reading bit line RBL (/WWL and /RWL respectively represent WWL and RWL shown in figures). The memory cell has CMOS inverter 15, 16 and 17 and transmission gates 18, 19 and 20. The transmission gates 18, 19 and 20 are respectively formed of a set composed of a pMOS transistor 21 and an nMOS transistor 24, a set composed of a a pMOS transistor 22 and an nMOS transistor 25 and a set composed of a pMOS transistor 23 and an nMOS transistor 26.
In this memory cell, in the writing operation, the writing word line WWL is at a high level "H", the writing word line/WWL is at a low level "U", the reading word line RWL is at the low level "L" and the reading word line /RWL is at the high level "H", so that the transmission gate 18 is in an on state "ON" and the transmission gates 19 and 20 are in an off state "OFF".
In a case where data "H" having the high level is written in the memory cell, after the writing bit line WBL is made to be at the high level "H" so that a node 27 is changed to the high level "H" and a node 28 is changed to the low level "L", the writing word lines WWL and /WWL are respectively changed to the low level "L" and the high level "H", so that the transmission gate 18 is turned off (the off state "OFF") and the transmission gate 19 is turned on (the on state "ON"). As a result, the CMOS inverters 15 and 16 form a flip flop circuit, so that the nodes 27 and 28 are respectively at the high level "H" and the low level "L". That is, the data "H" having the high level is stored in the memory cell.
On the other hand, in a case where data "L" having the low level "L" is written in the memory cell, after the writing bit line WBL is made to be at the low level "L" so that the nodes 27 and 28 are respectively made to be at the low level "L" and the high level "H", the writing word lines WWL and /WWL are respectively turned to the low level "L" and the high level "H", so that the transmission gate 18 is turned off (the off state "OFF") and the transmission gate 19 is turned on (the on state "ON"). As a result, the CMOS inverter form a flip flop, so that the nodes 27 and 28 are respectively at the low level "L" and the high level "H". That is, the data "U" having the low level is stored in the memory cell.
In addition, in the reading operation, the writing word line WWL is at the low level "L", the writing word line /WWL is at the high level "H", the reading word line RWL is at the high level "H" and the reading word line /RWL is at the low level "L", so that the transmission gate 18 is in the off state "OFF" and the transmission gates 19 and 20 are in the on state "ON". As a result, the memory cell in the reading operation can be represented by an equivalent circuit as shown in FIG. 3. In this case, when the data "H" having the high level is written in the memory cell, that is, when the nodes 27 and 28 are respectively at the high level "H" and the low level "U" as shown in FIG. 4, the reading bit line RBL is at the high level "H". On the other hand, when the data "L" having the low level is written in the memory cell, that is, when the nodes 27 and 28 are respectively at the low level "L" and the high level "H" as shown in FIG. 5, the reading bit line RBL is at the low level "L".
In the SRAM having the above structure, if each row address signal has n bits, a set of row address memory cells can be identified by each row address signal among 2.sup.n sets of row address memory cells. If only 2.sup.i (i is less than n) sets of row address memory cells are actually included in the memory matrix 2, there may be a case where a set of row address memory cells identified by a row address signal is not included in the memory matrix 2, since the number (2.sup.n) of sets of row address memory cells which can be identified by the row address having n bits is greater than the number (2.sup.i) of sets of row address memory cells actually included in the memory matrix 2. In this case, the following problem occurs.
The sense amplifier 7 is formed of a CMOS inverter as shown in FIG. 6. That is, the CMOS inverter is formed of a pMOS transistor 29 and a nMOS transistor 30 both of which are serially connected to each other between a high voltage power line VCC and a low voltage power line VSS. If a row address signal identifying a set of row address memory cells which is not included in the memory matrix 2 is supplied to the memory matrix 2, the reading bit line RBL connected to the sense amplifier 7 is in a floating state. As a result, a current I.sub.A passes through the CMOS inverter forming the sense amplifier 7, as shown in FIG. 6. This current I.sub.A is referred to as a through current. This through current I.sub.A causes the dissipation power to be increased, the deterioration of characteristics of the transistors to be accelerated, the DC test to be disturbed and the like. As a result, the above described advantages of using the CMOS inverter as the sense amplifier are canceled.
To solve the above problem, it may be proposed that a bus driver stack circuit, which is a kind of latch circuit, is connected to the reading bit line RBL, as shown in FIG. 7.
Referring to FIG. 7, memory cells 31 and 32, which are identified by different row address, are connected to the reading bit line RBL. A CMOS inverter 33 forming the sense amplifier 7 and a bus driver stack circuit 34 formed of CMOS inverters 35 and 36 are also connected to the reading bit line RBL. The bus driver stack circuit 34 controls the reading bit line RBL so that the reading bit line RBL is maintained at either the high level "H" or the low level "L" even if a row address identifying a set of row address memory cells which are not included in the memory matrix 2 is supplied to the memory matrix 2. That is, the reading bit line RBL is always maintained in a state which is not the floating state. As a result, no through current I.sub.A pass through the CMOS inverter 33.
If the data "H" having the high level is read, for example, from the memory cell 31, the outputs of the CMOS inverters 35 and 36 of the bus driver stack circuit 34 are respectively at the low level "L" and the high level "H" so that an input/output node 37 in the bus driver stack circuit 34 is fixed at the high level "H". As result, until the next reading operation is performed, the reading bit line RBL is maintained at the high level "H". On the other hand, if the data "L" having the low level is read from the memory cell 31, the outputs of the CMOS inverters 35 and 36 are respectively at the high level "H" and the low level "L" so that the input/output node 37 is fixed at the low level "L". As a result, until the next reading operation is performed, the reading bit line RBL is maintained at the low level "L".
As has been described above, in a case where the bus driver stack circuit 34 is used, the reading bit line RBL can be always maintained at either the high level "H" or the low level "L". Thus, even if a row address signal identifying a set of row address memory cells which are not included in the memory matrix 2 is supplied to the memory matrix 2, the reading bit line RBL is not in the floating sate, so that the through current I.sub.A does not pass through the CMOS inverter 33 forming the sense amplifier 7.
However, the SRAM having the bus driver stack circuit 34 as shown in FIG. 7, when the data "H" is read out from the memory cell 31 so that the reading bit line RBL is maintained at the high level "H" and the data "L" is then read out from the memory cell 32, a new problem occurs.
This problem will be described below with reference to FIG. 8. Referring to FIG. 8, the memory cell 32 is formed of CMOS inverter 38, 39 and 40 which correspond to the CMOS inverter 15, 16 and 17 shown in FIG. 2. The CMOS inverter 40 is formed of a pMOS transistor 41 and an nMOS transistor 42, and the CMOS inverters 38 and 39 have the same structure as the CMOS inverter 40. Transmission gates corresponding to the transmission gates 18, 19 and 20 shown in FIG. 2 are omitted from the FIG. 8. In the bus driver stack circuit 34, the CMOS inverter 36 is formed of a pMOS transistor 43 and an nMOS transistor 44, and the CMOS inverter 35 has the same structure as the CMOS inverter 36.
If the reading bit line RBL is maintained at the high level "H", in the bus driver stack circuit 34, the output of the CMOS inverter 35 is at the low level "L" so that the pMOS transistor 43 is in the on state "ON" and the nMOS transistor 44 is in the off state "OFF". IN addition, if data "L" is stored in the memory cell 32, nodes 45 and 46 in the memory cell 32 are respectively at the low level "L" and the high level "H" so that the pMOS transistor 41 is in the off state "OFF" and the nMOS transistor 42 is in the on state "ON". Thus, in a case where the data "L" is read out from the memory cell 32, a current I.sub.B flows from the reading bit line RBL to the low voltage power line VSS through the nMOS transistor 42 in the memory cell 32, so that the level of the reading bit line RBL is decreased down from the high level "H" to the low level "L". In this case, a current I.sub.C is supplied from the high voltage power line VCC to the reading bit line RBL through the pMOS transistor 43 in the bus driver stack circuit 34. As a result, a time needed to decrease the level of the reading bit line RBL from the high level "H" to the low level "L" is increased.
In addition, when the data "U" is read out from the memory cell 31 so that the reading bit line RBL is maintained at the low level "L" and the data "H" is then read out from the memory cell 32, the same problem occurs.
This problem will be described below with reference to FIG. 9. Referring to FIG. 9, if the reading bit line RBL is maintained at the low level "L", in the bus driver stack circuit 34, the output of the CMOS inverter 35 is at the high level "H" so that the pMOS transistor 43 is in the off state "OFF" and the nMOS transistor is in the on state "ON". In addition, if the data "H" is stored in the memory cell 32, the nodes 45 and 46 in the memory cell 32 are respectively at the high level "H" and the low level "L" so that the pMOS transistor 41 is in the on state "ON" and the nMOS transistor 42 is in the off state "OFF". Thus, when the data "H" is read out from the memory cell 32, a current I.sub.D is supplied from the high voltage power line VCC to the reading bit line RBL through the pMOS transistor 41 in the memory cell 32, so that the level of the reading bit line RBL is pulled up from the low level "U" to the high level "H".
However, in this case, a current I.sub.E flows from the reading bit line RBL to the lower voltage power line VSS through the nMOS transistor in the bus driver stack circuit 34. As a result, a time needed to pull up the level of the reading bit line RBL from the low level "L" to the high level "H" is increased.
As has been described above, in the SRAM provided with the bus driver stack circuit 34 as shown in FIG. 7, when data having a potential level opposite to the potential level at which the read bit line RBL is maintained by the bus driver stack circuit 34 is read out from a memory cell, a time which is needed to invert the potential level of the read bit line RBL is increased. As a result, a reading rate cannot be increased.
In addition, in the SRAM as shown in FIG. 7, the output potential level of the memory cell 32 must exceed the output potential level of the CMOS inverter 36 in the bus driver stack circuit 34 so that a threshold voltage condition of the CMOS inverter 33 is satisfied. Thus, the margins of production process conditions of the SRAM and the operating margin of the SRAM with respect to a power voltage are narrow.